1. Field of the Invention
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors (MOSFETs), and, more particularly, to MOSFETs that achieve improved carrier mobility through the incorporation of strained silicon.
2. Related Technology
MOSFETs are a common component of integrated circuits (ICs). FIG. 1 shows a cross sectional view of a conventional MOSFET device. The MOSFET is fabricated on a silicon substrate 10 within an active region bounded by shallow trench isolations 12 that electrically isolate the active region of the MOSFET from other IC components fabricated on the substrate 10.
The MOSFET is comprised of a gate 14 and a channel region 16 that are separated by a thin gate insulator 18 such as silicon oxide or silicon oxynitride. A voltage applied to the gate 14 capacitively controls the creation of an inversion layer in the channel region 16 that provides carriers for conduction between the source and drain. To minimize the resistance of the gate 14, the gate 14 is typically formed of a doped semiconductor material such as polysilicon.
The source and drain of the MOSFET comprise deep source and drain regions 20 formed on opposing sides of the channel region 16. The deep source and drain regions 20 are formed by ion implantation subsequent to the formation of a spacer 22 around the gate 14. The spacer 22 serves as a mask during implantation to define the lateral positions of the deep source and drain regions 20 relative to the channel region 16.
Source and drain silicides 24 are formed on the deep source and drain regions 20 to provide ohmic contacts and reduce contact resistance. The silicides 24 are comprised of the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni). The deep source and drain regions 20 are formed deeply enough to extend beyond the depth to which the source and drain suicides 24 are formed. The gate 14 likewise has a silicide 26 formed on its upper surface. A gate structure comprising a polysilicon material and an overlying silicide is sometimes referred to as a polycide gate.
The source and drain of the MOSFET further comprise shallow source and drain extensions 28. As dimensions of the MOSFET are reduced, short channel effects resulting from the small distance between the source and drain cause degradation of MOSFET performance. The use of shallow source and drain extensions 28 rather than deep source and drain regions near the ends of the channel 16 helps to reduce short channel effects. The shallow source and drain extensions 28 are implanted after the formation of a protective layer 30 around the gate 14 and over the substrate, and prior to the formation of the spacer 22. The gate 14 and the protective layer 30 act as an implantation mask to define the lateral position of the shallow source and drain extensions 28 relative to the channel region 16. Diffusion during subsequent annealing causes the shallow source and drain extensions 28 to extend slightly beneath the gate 14.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is more widely spaced on average than a pure silicon lattice because of the presence of the larger germanium atoms in the lattice. Since the atoms of the silicon lattice align with the more widely spaced silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
The tensile strain applied to the silicon lattice increases carrier mobility. Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET incorporating a strained silicon layer is shown in FIG. 2. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 grown on a silicon layer 10. An epitaxial layer of strained silicon 34 is grown on the silicon germanium layer 32. The MOSFET uses conventional MOSFET structures including deep source and drain regions 20, shallow source and drain extensions 28, a gate oxide layer 18, a gate 14 surrounded by a protective layer 30, a spacer 22, source and drain silicides 24, a gate silicide 26, and shallow trench isolations 12. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
An alternative to the formation of devices in semiconductor substrates is silicon on insulator (SOI) construction. In SOI construction, MOSFETs are formed on a substrate that includes a layer of a dielectric material beneath the MOSFET active regions. SOI devices have a number of advantages over devices formed in a shared semiconductor substrate, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
FIG. 3 shows an example of a strained silicon MOSFET formed on an SOI substrate. In this example, the MOSFET is formed on an SOI substrate that comprises a silicon germanium layer 32 provided on a dielectric layer 36. The MOSFET is formed within an active region defined by trench isolations 12 that extend through the silicon germanium layer 32 to the underlying dielectric layer 36. In one alternative to the SOI structure of FIG. 3, strained silicon FinFETs comprised of monolithic silicon germanium FinFET bodies having strained silicon grown thereon may be formed from the silicon germanium SOI substrate. An alternative type of SOI MOSFET, known as a FinFET, is formed by patterning monolithic semiconductor bodies comprising source, drain and channel regions from a semiconductor layer formed on a dielectric substrate.
The substrate for a conventional SOI device may be formed in a variety of manners. FIGS. 4a-4b show structures formed using a buried oxide (BOX) method for forming an SOI substrate. As shown in FIG. 4a, a silicon substrate 40 is provided. The silicon substrate 40 is implanted with oxygen 42 at an energy sufficient to form an oxygenated region 44 at such a depth as to leave a required thickness of silicon above the oxygenated region. FIG. 4b shows the structure of FIG. 4a after annealing of the silicon substrate 40 to form a buried silicon oxide layer 46 within the substrate. Annealing is typically performed at approximately 1350 degrees C. for approximately four hours. The oxide layer 30 serves as the dielectric layer of the SOI substrate.
FIGS. 5a-5d show structures formed in accordance with a wafer bonding method for forming an SOI substrate. FIG. 5a shows a planarized silicon substrate 48. The substrate 48 is implanted with hydrogen 50 to form a hydrogen rich region 52 within the silicon material. The hydrogen 50 is implanted with an energy such that the amount of silicon remaining above the hydrogen rich region exceeds the thickness of the silicon layer to be formed on the SOI substrate. In some applications a different material such as oxygen may be implanted.
FIG. 5b shows the silicon substrate 48 of FIG. 5a after being cleaned, stripped of oxide in a diluted HF solution, rinsed in deionized water to form an active native oxide on its surface, and then inverted and bonded to a planarized oxide layer 56 formed on a semiconductor layer 58 of second substrate 54. To facilitate bonding, adjoining surfaces of the substrates are planarized to a homogeneity of 0.5 microns or less. Bonding is generally performed in two stages. In a first stage, the substrates are heated to approximately 600 degrees C. in an inert environment for approximately three hours. As shown in FIG. 5c, the heating of the first stage causes bonding of the silicon substrate 48 to the dielectric layer 56 of the second substrate 54 due to Van der Waals forces. The heating of the first stage also causes the first substrate 48 to fracture in the hydrogen rich region 52. After the first heating stage the fractured portion of the first substrate is removed, leaving a new substrate comprising a silicon layer 59 bonded to an oxide layer 56, and having a residual hydrogen rich region 52 at its upper surface.
In a second stage of the bonding process, the bonded structure is heated to approximately 1050-1200 degrees C. for 30 minutes to two hours to strengthen the bond between the dielectric layer 56 and the silicon layer 59. The resulting substrate is then planarized and cleaned, leaving a silicon SOI substrate as shown in FIG. 5d. Where it is desired to form strained silicon SOI devices, a silicon germanium SOI substrate may be formed instead of a silicon SOI substrate, and strained silicon may then be grown on the silicon germanium.
One detrimental property of strained silicon devices and SOI devices is that they have poor thermal conductivity compared to conventional devices formed in silicon substrates. Heat generated in the active region of a MOSFET formed in a silicon substrate is conducted away from the active region through the silicon substrate, which has a relatively good thermal conductivity of 1.5 W/cm-C°. In contrast, the thermal conductivity of a typical silicon germanium layer used in a strained silicon device is approximately 0.1 W/cm-C° for a silicon germanium layer having a 20% germanium content, which results in significantly less efficient dissipation of heat to the underlying silicon layer. Further, the oxide layer of an SOI substrate has a very poor thermal conductivity of less than 0.02 W/cm-C°. As a result, insufficient dissipation of thermal energy can occur in strained silicon devices and particularly in strained silicon SOI devices, leading to significant self-heating. Self-heating is known to degrade the I-V characteristics of the MOSFET, such that a reduced source-drain current Ids is produced for a given source-drain voltage Vds.
Therefore the advantages of strained silicon MOSFETs and MOSFETs formed by SOI construction are partly offset by the disadvantages resulting from the poor thermal conductivity of silicon germanium and oxide layers.